Manufacturing method of circuit carrier board

ABSTRACT

A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the prioritybenefit of U.S. application Ser. No. 16/503,500, filed on Jul. 04, 2019,now allowed, which claims the priority benefits of Taiwan applicationserial no. 108115660, filed on May 7, 2019. The prior U.S. applicationSer. No. 16/503,500 is a continuation-in-part application of and claimsthe priority benefit of U.S. application Ser. No. 16/244,113, filed onJan. 10, 2019, now patented. The prior U.S. application Ser. No.16/244,113 claims the priority benefit of U.S provisional applicationSer. No. 62/682,181, filed on Jun. 8, 2018, and Taiwan applicationserial no. 107136704, filed on Oct. 18, 2018. The entirety of each ofthe above-mentioned patent applications is hereby incorporated byreference herein and made a part of this specification.

BACKGROUND Technical Field

The present invention relates to a manufacturing method of a circuitcarrier board.

Description of Related Art

In general, the multilayer circuit structure of a circuit board ismostly manufactured by a build-up method or a laminated method, and thushas the features of high circuit density and reduced circuit spacing.For example, the multilayer circuit structure is formed by combining acopper foil and a PrePreg into a build-up layer structure and stackingthe build-up layer structure on a core layer via repeated lamination toincrease the internal wiring space of the multilayer circuit structure,wherein the conductive material on the build-up layer structure may formconductive circuits according to the required circuit layout, and theblind vias or through-holes of the build-up layer structure may beadditionally filled with a conductive material to conduct each of thelayers. Thus, the multilayer circuit structure may be manufactured byadjusting the number of circuit structures according to requirements andvia the above method.

With the advancement of technology, all kinds of electronic products aredeveloped to have high speed, high efficiency, and be compact. Underthis trend, how to design circuit boards to enable a plurality of chipswith high-density circuits to communicate with each other, and improvesignal transmission efficiency between the chips, is an urgent problemto be solved in the field.

SUMMARY

The invention provides a circuit carrier board and a manufacturingmethod thereof, which are adapted to interconnect electronic elementswith a plurality of high density circuits, reducing signal delay andimproving performance of the circuit carrier board.

The manufacturing method of the circuit carrier board of the inventioncomprises the following steps. A first temporary carrier board isprovided. A first substrate is formed on the first temporary carrierboard. The first substrate includes a first circuit layer and aplurality of conductive structures, and the conductive structures areadapted to be electrically connected to the plurality of electronicelements. A bonding step is performed so as to bond the first substrateto the second temporary carrier board. The conductive structures arelocated between the first circuit layer and the second temporary carrierboards. The first temporary carrier board is removed. A second substrateis formed on the first substrate to bond the second substrate to thefirst substrate. The second substrate includes a plurality of dielectriclayers and a plurality of second circuit layers, and the second circuitlayers are disposed in the dielectric layer. The bottommost layer of thesecond circuit layers is exposed outside of the dielectric layer, andthe topmost layer of the second circuit layers is electrically connectedto the first circuit layer. And, the second temporary carrier board isremoved.

In an embodiment of the invention, the step of forming the firstsubstrate includes forming a release layer on the first temporarycarrier board. The first circuit layer is formed on the release layer.An insulating layer is formed on the release layer and covers the firstcircuit layer. A conductive structure is formed on the insulating layer,and the conductive structure is electrically connected to the firstcircuit layer. An insulating adhesive material is formed on theinsulating layer, and the conductive structure is located between theinsulating adhesive material and the insulating layer.

In an embodiment of the invention, the step of forming the firstsubstrate further includes performing a thinning process to remove aportion of the insulating adhesive material to form an insulatingadhesive layer and exposing the conductive structure.

In an embodiment of the invention, the step of forming the secondsubstrate includes forming the dielectric layers stacked on the firstsubstrate in sequence. The second circuit layers are formed in thedielectric layers, and the second circuit layers are electricallyconnected to one another.

In an embodiment of the invention, the step of forming the firstsubstrate includes forming the release layer on the first temporarycarrier board. The first circuit layer is formed on the release layer.And the insulating adhesive material is formed on the first circuitlayer.

In an embodiment of the invention, the step of forming the firstsubstrate further includes: after the step of forming the secondsubstrate on the first substrate, a plurality of contact windows areformed in the insulating adhesive material to form the insulatingadhesive layer. The conductive structure is formed in the insulatingadhesive layer, and the conductive structure is electrically connectedto the first circuit layer through the contact windows.

In an embodiment of the invention, the manufacturing method of thecircuit carrier board further includes forming a plurality of solderresist layers on the first substrate and the second substraterespectively. The solder resist layers partially cover the conductivestructures and the bottommost layer of the second circuit layers. Aplurality of solder balls are disposed and electrically connected to thebottommost layer of the second circuit layers.

Based on the above, in the manufacturing method of the circuit carrierboard of the invention, the second substrate having a normal linewidthcan be directly formed and bonded to the entire surface of the firstsubstrate having the first circuit layer with the ultra-fine linewidth.Therefore, the first circuit layer and the second circuit layer made ofdifferent fineness in linewidth can be directly integrated onto thecircuit carrier board, which simplifies the process, reduces the cost,and improves the wiring margin. In addition, a plurality of electronicelements having high density circuits can be directly electricallyconnected to the conductive structures of the first substrate, and thusthe electronic elements can achieve interconnectivity through the firstcircuit layer. In this way, signal delay between interconnectedelectronic elements can be reduced and the performance of the circuitcarrier board can be improved. In addition, the plurality of build-uplayers of the second substrate can support the first substrate, therebyimproving the overall rigidity and the reliability of the structure ofthe circuit carrier board.

To make the aforementioned more comprehensible, several embodimentsaccompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate exemplaryembodiments of the disclosure and, together with the description, serveto explain the principles of the disclosure.

FIG. 1A to FIG. 1K are cross-sectional views showing a manufacturingprocess of a circuit carrier board of an embodiment of the invention.

FIG. 2A is a partial top view showing the top surface of the pad in theregion R of FIG. 1A.

FIG. 2B is a partial top view of the bottom surface of the conductivevia and the first circuit layer in the region R of FIG. 1A.

FIG. 3A to FIG. 3K are cross-sectional views showing a manufacturingprocess of a circuit carrier board of another embodiment of theinvention.

FIG. 4 is a cross-sectional view of a circuit carrier board of yetanother embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Some embodiments are provided hereinafter and described in detail withreference to figures. However, the embodiments provided are not intendedto limit the scope of the invention. Moreover, the figures are onlydescriptive and are not drawn to scale. For ease of explanation, thesame devices below are provided with the same reference numerals.

Moreover, terms such as “first” and “second” used herein do notrepresent order, and it should be understood that they are fordifferentiating devices or operations having the same technical terms.

Secondly, the terms “containing”, “including”, “having” and the like asused herein are all open terms; i.e., including but not limited to.

Furthermore, the terms “in contact with”, “connected to”, “bonded to”and the like, as used herein, may mean direct contact or indirectcontact via other layers unless otherwise stated.

FIG. 1A to FIG. 1K are cross-sectional views showing a manufacturingprocess of a circuit carrier board of an embodiment of the invention.Referring to FIG. 1K first, in the present embodiment, the circuitcarrier board 1 includes a first substrate 100 and a second substrate200, which is bonded to the first substrate 100. The first substrate 100includes a first circuit layer 110 and a plurality of conductivestructures 130 electrically connected to the first circuit layer 110.The conductive structures 130 are adapted to be electrically connectedto the plurality of electronic elements 300 disposed on the firstsubstrate 100. The second substrate 200 contacts the first circuit layer110, and includes a plurality of dielectric layers 220 sequentiallystacked on the first substrate 100, and a plurality of second circuitlayers 210 are disposed in the dielectric layers 220. The bottommostlayer 212 of the second circuit layers 210 is exposed to be outside ofthe dielectric layer 220, and the topmost layer 211 of the secondcircuit layers 210 is electrically connected to the first circuit layer110. The circuit carrier board 1 further includes a plurality of solderresist layers SR respectively disposed on the first substrate 100 andthe second substrate 200, and a plurality of solder balls SB disposed onthe second substrate 200 to be electrically connected to the bottommostlayer 212 of the second circuit layers 210. The following descriptionwill briefly explain the manufacturing method of the circuit carrierboard 1 according to an embodiment.

Referring to FIG. 1A, FIG. 1B and FIG. 1C, the manufacturing method ofthe circuit carrier board 1 (shown in FIG. 1K) includes the followingsteps. First, as shown in FIG. 1A, a first temporary carrier board 10 isprovided.

Next, a first substrate 100′ (shown in FIG. 1C) is formed on the firsttemporary carrier board 10. In the present embodiment, the firstsubstrate 100′ may be a single layer or a stacked structure ofmultilayer. As shown in FIG. 1A, the step of forming the first substrate100′ includes forming a release layer 12 on the first temporary carrierboard 10 first, and then the first wiring layer 110 is formed on therelease layer 12. The release layer 12 may be a photo-curable releasefilm or a thermal curable release film, but the invention is not limitedthereto. The viscosity of the photo-curable release film is reduced by aphoto-curing process; and the viscosity of the thermal curable releasefilm is reduced by thermal-curing process. In other embodiments, therelease layer 12 may also be a laser debond release film.

In the present embodiment, the first circuit layer 110 is disposed by anultra-fine line process. For example, the linewidth D1 of the firstcircuit layer 110 (shown in FIG. 2B) may be less than or equal to 5microns. In some embodiments, the linewidth D1 of the first circuitlayer 110 may be selectively between 1 micron and 5 microns, but theinvention is not limited thereto. Under the above arrangement, the firstcircuit layer 110 can meet the demand of ultra-fine lines. Based onconductivity considerations, the first circuit layer 110 is generallymade of a metal material, for example, including copper, aluminum,silver, gold, or other suitable materials, but the invention is notlimited thereto. According to other embodiments, the first circuit layer110 may also use other conductive materials such as including an alloy,an oxide of a metal material, a nitride of a metal material, anoxynitride of a metal material, or stacked layers of a metal materialand other conductive materials. In the present embodiment, the method offorming the first circuit layer 110 includes electroplating or chemicalplating (or known as electroless plating), but the invention is notlimited thereto.

Then, referring to FIG. 1B, a plating process is performed to form theinsulating layer 120 on the release layer 12 and cover the first circuitlayer 110. In other words, the insulating layer 120 and the first wiringlayer 110 can be used as one of the build-up layers in the multilayerstructure of the first substrate 100′. In some embodiments, the build-uplayers combined by the first circuit layer 110 and the insulating layer120 may be sequentially stacked to form a build-up of two, three or morelayers. The plurality of first circuit layers 110 in the multilayerbuild-up layer can be electrically connected to one another through aplurality of through holes penetrating the insulating layer 120. FIG. 1Bof the embodiment is illustrated with only one layer of the firstcircuit layer 110 and one layer of the insulating layer 120 for claritypurpose. In fact, the number of the first circuit layer 110 and theinsulating layer 120 is not limited by the number shown in FIG. 1B.

Next, a plurality of contact windows 122 are formed on the insulatinglayer 120 to expose a portion of the first circuit layer 110. Then,conductive structures 130 are formed on the insulating layer 120, andthe conductive structures 130 may be filled in the contact windows 122to be electrically connected to the first circuit layer 110. In thepresent embodiment, the material of the insulating layer 120 comprises adielectric material not including a glass fiber cloth, for example, thematerial can be selected from the group consisting of Ajinomoto build-upfilm (ABF), adhesive, and photosensitive dielectric material(photoimageable dielectric, PID) or a photosensitive polymer (such asbenzocyclobutene) or a combination thereof, but the invention is notlimited thereto. In some embodiments, the material of the insulatinglayer 120 may also include a dielectric material with adhesiveness, forexample, including an epoxy resin, but the invention is not limitedthereto. In the present embodiment, the method of forming the pluralityof contact windows 122 includes photolithography, mechanical drilling,laser drilling, or other suitable methods, the invention is not limitedthereto.

In detail, a portion of the conductive structure 130 is formed on theinsulating layer 120, and another portion is formed in the insulatinglayer 120. As shown in FIG. 1B, the conductive structure 130 may includepads 132 and conductive vias 134 electrically connected to the pads 132.The pads 132 are disposed on the insulating layer 120, and theconductive vias 134 are filled in the contact windows 122. In thismanner, the pads 132 on the insulating layer 120 can be electricallyconnected to the portion of the first circuit layer 110 exposed by thecontact windows 122 through the conductive vias 134 in the insulatinglayer 120. In the present embodiment, a portion of the pads 132 may alsonot contact the conductive vias 134 and serve as structures thatinterconnect other conductive structures 130 located in the same plane.The above-mentioned portion of the pads 132 and the pads 132 connectedto the conductive vias 134 can be formed through the same patterningprocess, and thus can be regarded as a part of the conductive structure130, but the invention is not limited thereto. In other words, in someembodiments, the structures that horizontally interconnect theconductive vias 134 can also be completed in additional steps as needed.

In the present embodiment, based on conductivity considerations, theconductive structure 130 (including the pads 132 and the conductive vias134) generally includes a metal or a metal alloy such as molybdenum,aluminum, titanium, copper, gold, silver or other metal conductivematerials or a stack of two or more of the above materials or an alloyof two or more of the above materials, the invention is not limitedthereto. In the present embodiment, the method of forming the conductivestructure 130 includes electroplating or chemical plating, but theinvention is not limited thereto. In some embodiments, the conductivestructure 130 may also be formed by Physical Vapor Deposition (PVD),Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

Then, referring to FIG. 1C, an insulating adhesive material 140′ isformed on the insulating layer 120 and covers the conductive structure130 and the insulating layer 120. In other words, the conductivestructure 130 may be located between the insulating adhesive material140′ and the insulating layer 120. So far, the manufacturing of thefirst substrate 100′ that has not exposed the pads 132 is substantiallycompleted. That is, the first substrate 100′ is an ultra-fine linecircuit substrate that includes a build-up layer of the first circuitlayer 110 and the insulating layer 120, the conductive structures 130electrically connected to the first circuit layer 110, and an insulatingadhesive material 140′ covering the conductive structure 130. Fromanother point of view, the first substrate 100′ is, for example, aredistribution layer (RDL) using ultra-fine line technology, but theinvention is not limited thereto. In the present embodiment, thematerial of the insulating adhesive material 140′ comprises athermosetting polymer or a photopolymer. The thermosetting polymerincludes, for example, a polyester resin, a polyurethanes, a melamineresin, an Ajinomoto build-up film (ABF), an epoxy resin, a polyimides, asilicone or a vinyl ester. A photopolymer includes, for example, anacrylate or an epoxy resin. However, the invention is not limitedthereto.

Next, referring to FIG. 1D, a bonding step is performed to bond thefirst substrate 100′ to the second temporary carrier board 20. In thepresent embodiment, metal layers 21 are disposed on the two oppositesurfaces of the second temporary carrier board 20, and the releaselayers 22 are respectively disposed on the two metal layers 21. As shownin FIG. 1D, the insulating adhesive material 140′ of the first substrate100′ is bonded to the release layer 22 on the second temporary carrierboard 20. In addition, the conductive structure 130 is located betweenthe first circuit layer 110 and the second temporary carrier board 20.From another perspective, the first circuit layer 110 is located on asurface 101 of the insulating layer 120 away from the second temporarycarrier board 20. In fact, the first circuit layer 110 is embedded onthe surface 101 of the insulating layer 120. In addition, the pad 132may be disposed on the other surface 103 of the insulating layer 120opposite to the surface 101, and the insulating adhesive material 140′is disposed on the other surface 103 to cover the pad 132, but theinvention is not limited thereto.

In the present embodiment, the second temporary carrier board 20 may bea glass substrate, a silicon substrate (Si substrate), a ceramicsubstrate, or a combination thereof, but the invention is not limitedthereto. The material of the metal layer 21 is, for example, a metal oran alloy, including aluminum, copper, silver, gold or an alloy of theabove metals or other suitable materials, and the invention is notlimited thereto. From another point of view, the second temporarycarrier board 20 is, for example, a double-sided copper clad laminate(CCL) substrate, but the invention is not limited thereto. In thepresent embodiment, the release layer 22 may be a photo-curable releasefilm or a thermal curable release film, but the invention is not limitedthereto. In other embodiments, the release layer 22 may also be a laserdebond release film.

In the present embodiment, as shown in FIG. 1D, two first substrates100′ (such as a top first substrate 100′ and a bottom first substrate100′) can be simultaneously bonded to the second temporary carrier board20, so that in the subsequent steps, the second substrate 200 (shown inFIG. 1G) may be formed on the first substrate 100′ at the top and on thefirst substrate 100′ at the bottom simultaneously. In this way, themanufacturing process can be simplified and the production cost can bereduced. The following steps will be mainly described by the firstsubstrate 100′ below the second temporary carrier board 20. It should beunderstood by those skilled in the art that the first substrate 100′located above the second temporary carrier board 20 is the same as theprocess steps performed by the first substrate 100′ below, thereforedetails are not repeated herein.

Then, referring to FIG. 1D and FIG. 1E, the first temporary carrierboard 10 and the release layer 12 formed on the first temporary carrierboard 10 are removed to expose the first circuit layer 110. The methodof removing the first temporary carrier board 10 includes, for example,reducing the viscosity of the release layer 12 by illumination, heating,or by laser dissociation, thereby separating the first temporary carrierboard 10 from the first substrate 100′.

Next, referring to FIG. 1F and FIG. 1G, the second substrate 200 isformed on the first substrate 100′. In the present embodiment, thesecond substrate 200 includes a plurality of build-up layers formed bysequentially stacking a plurality of dielectric layers 220 and aplurality of second circuit layers 210 on the first substrate 100′. Forexample, as shown in FIG. 1F and

FIG. 1G, the step of forming the second substrate 200 includessequentially stacking the plurality of dielectric layers 220 on thefirst substrate 100′. One of the dielectric layers 220 is disposed onthe surface 101 of the insulating layer 120. That is, in thisembodiment, the second substrate 200 is disposed on the insulating layer120. Then, the plurality of the second circuit layers 210 are formed inthe dielectric layers 220, and the second circuit layers 210 located atdifferent horizontal film layers are electrically connected to oneanother. In another aspect, each of the second circuit layers 210 andeach of the dielectric layers 220 may define a single build-up layer ofthe second substrate 200, and the plurality of the above-mentionedbuild-up layers may be sequentially stacked on the first substrate 100′so as to form the second substrate 200. In the present embodiment, thesecond substrate 200 includes, for example, two of the above-mentionedbuild-up layers, but the invention is not limited thereto. In someembodiments, the second substrate 200 may also include one, or three ormore build-up layers, and is not limited to the number shown in FIG. 1G.The following description will be made with the second substrate 200including two build-up layers of one upper build-up layer and one lowerbuild-up layer.

In the present embodiment, as shown in FIG. 1F and FIG. 1G, the upperbuild-up layer (not labeled) may be defined as the topmost dielectriclayer 220 and the second circuit layer 210 in the topmost dielectriclayer 220 that contacts the first substrate 100′. The topmost dielectriclayer 220 may form a plurality of contact windows (not labeled) toexpose portions of the first circuit layer 110. A second circuit layer210 formed on the topmost dielectric layer 220 may be filled in thecontact windows to be electrically connected to the first circuit layer110. In the present embodiment, as shown in FIG. 1F and FIG. 1G, thesecond circuit layer 210 electrically connected to the first circuitlayer 110 may be defined as the topmost layer 211 of the second circuitlayer 210.

Then, the lower build-up layer (not labeled) is stacked on the surfaceof the upper build-up layer. For example, the lower build-up layer canbe defined as the bottommost dielectric layer 220 and the second circuitlayer 210 in the bottommost dielectric layer 220 that contacts the upperbuild-up layer. The bottommost dielectric layer 220 may form a pluralityof contact windows (not labeled) to expose portions of the topmost layer211. The second circuit layer 210 formed on the bottommost dielectriclayer 220 may be filled in the contact windows to be electricallyconnected to the topmost layer 211. In the present embodiment, as shownin FIG. 1G, the second circuit layer 210 electrically connected to thetopmost layer 211 can be defined as the bottommost layer 212 of thesecond circuit layer 210, and the above-mentioned bottommost layer 212can be exposed to be outside of the bottommost dielectric layer 220.

In the present embodiment, the material of the dielectric layer 220includes a PrePreg, a photosensitive dielectric material (such as aPID), a photosensitive polymer (for example, benzocyclobutene), an ABF.Build-up film), a resin coated cooper foil (RCC), a fiberglass resincomposite or a combination thereof, but the invention is not limitedthereto.

In this embodiment, portions of the plurality of second circuit layers210 may penetrate through the dielectric layers 220 to electricallyconnect the second circuit layers 210 of different horizontal planes toeach other, and another portion of the second circuit layers 210 areonly interconnected to the second circuit layer 210 located on the samehorizontal plane. In other words, the second circuit layer 210 canprovide the need for the horizontal and vertical trace interconnectionthat is required for the second substrate 200.

In the present embodiment, the second circuit layer 210 can be disposedby a process of a normal trace requirement or by a process of a highdensity trace requirement. For example, the linewidth of the secondcircuit layer 210 may be 5 microns to hundreds of microns, but theinvention is not limited thereto. In some embodiments, the thinnestlinewidth of the second circuit layer 210 may selectively be 8 micronsto 25 microns, but the invention is not limited thereto. Based onconductivity considerations, the second circuit layer 210 is generallymade of a metal material, for example, including copper, aluminum,silver, gold, or other suitable materials, but the invention is notlimited thereto. According to other embodiments, the second wiring layer210 may also use other conductive materials including an alloy, an oxideof a metal material, a nitride of a metal material, an oxynitride of ametal material, or a stacked layers of a metal material and otherconductive materials. In the present embodiment, the method of formingthe second circuit layer 210 includes electroplating or chemicalplating, but the invention is not limited thereto.

Then, referring to FIG. 1G and FIG. 1H, the second temporary carrierboard 20 is removed to separate the release layer 22 from the secondtemporary carrier board 20. The method of removing the second temporarycarrier board 20 includes, for example, reducing the viscosity of therelease layer 22 by illumination, heating or by laser dissociation,thereby separating the metal layer 21 on the second temporary carrierboard 20 from the release layer 22. So far, the steps of manufacturingthe second substrate 200 and bonding the second substrate to the firstsubstrate 100′ is substantially completed. That is, the second substrate200 is a circuit board with two build-up layers, each including a secondcircuit layer 210 and a dielectric layer 220. In the present embodiment,the second substrate 200 having the second circuit layer 210 is, forexample, a substrate applying the technologies of a high densityinterconnect (HDI) board, a coreless substrate, or an any-layer printedcircuit board.

It should be noted that, the embodiment can directly dispose the secondsubstrate 200 with normal linewidths, which indicates that the secondsubstrate 200 does not apply the ultra-fine line technology, on thefirst substrate 100′ having the first circuit layer 110 with ultra-finelines. In this way, the present invention can directly connect the firstcircuit layer 110 having a smaller linewidth to the second circuit layer210 having a larger linewidth by a simple process. Therefore, themanufacturing process can be simplified and the cost can be reduced.

Next, referring to FIG. 1H and FIG. 1I, in the present embodiment, thestep of forming the first substrate 100 further includes performing athinning process. The thinning process described above may remove aportion of the insulating adhesive material 140′ to form the insulatingadhesive layer 140 and expose the pads 132 of the conductive structures130. In thie embodiment, the release layer 22 may be removed prior tothe step of the thinning process. The method of removing the releaselayer 22 is similar to the method of removing the second temporarycarrier board 20, and therefore details are not repeated herein, but theinvention is not limited thereto. In some embodiments, the release layer22 may also be removed during the thinning process is being performed.

In the present embodiment, the thinning process includes the use of areactive ion-etching (RIE) process, a half tone mask (HTM), a gray tonemask, or a phase shift mask to perform a developing process to remove aportion of the insulating adhesive material 140′, but the invention isnot limited thereto. Under the above arrangement, the formed insulatingadhesive layer 140 may expose the pad 132 and partially contact thesidewall of the pad 132 (not labeled). In short, the first substrate100′ to which the pads 132 have not been exposed is subjected to athinning process to expose the pads 132, thereby completing thefabrication of the first substrate 100. In the present embodiment, theinsulating adhesive layer 140 surrounds and contacts the edge of the pad132 (as shown in FIG. 2A), and the pad 132 is partially exposed, thusthe pad 132 can be partially embedded in the insulating adhesive layer140. From another perspective, the pads 132 of the conductive structures130 have the insulating adhesive layer 140 therebetween. In this way,the insulating adhesive layer 140 not only may increase the structuralreliability of the pads 132, but also protect the pads 132 and theinsulating layer 120. In addition, the insulating adhesive layer 140 mayalso have a solder resist effect, and the step of disposing the solderresist layer SR may be omitted to simplify the manufacturing process andreduced the production cost.

Then, referring to FIG. 1J, a plurality of solder resist layers SR arerespectively formed on the first substrate 100 and the second substrate200. In the present embodiment, the two solder resist layers SRpartially cover the conductive structures 130 on the first substrate 100and the bottom layer 212 of the second circuit layers 210 on the secondsubstrate 200 respectively. For example, the solder resist layer SR onthe first substrate 100 and the solder resist layer SR on the secondsubstrate 200 may each have a plurality of contact windows (not labeled)to respectively expose the pads 132 and the bottom layer 212 of thesecond circuit layers 210. In the present embodiment, the materials ofthe solder resist layers SR include a green lacquer, a photosensitivedielectric material, an ABF, and a polymer resin material, but theinvention is not limited thereto.

Next, referring to FIG. 1J and FIG. 1K, a plurality of electronicelements 300 are disposed on the first substrate 100 to be electricallyconnected to the pads 132 and the first circuit layer 110. In thepresent embodiment, the electronic elements 300 are exemplified as awafer, but the invention is not limited thereto. As shown in FIG. 1K,the electronic elements 300 include, for example, a first electronicelement 310 and a second electronic element 320, and a plurality ofconductive bumps 311, 321 are disposed with high density on each of thefirst electronic element 310 and the second electronic element 320respectively. In the present embodiment, the first electronic element310 and the second electronic element 320 further include a plurality ofsolder balls 312, 322 respectively disposed on the conductive bumps 311,321, but the invention is not limited thereto. The first electronicelement 310 and the second electronic element 320 are electricallyconnected to the pad 132 through the conductive bumps 311, 321 and thesolder balls 312, 322. Based on conductivity considerations, theconductive bumps 311, 321 are generally made of a metal material oralloy, including copper, aluminum, silver, gold, or an alloy of two ormore of the above materials, or other suitable materials, but theinvention is not limited thereto.

Finally, a plurality of solder balls SB are disposed on the secondsubstrate 200 and electrically connected to the bottommost layer 212 ofthe second circuit layers 210. At this point, the manufacturing processof the circuit carrier board 1 has been completed.

FIG. 2A is a partial top view showing the top surface of the pad in theregion R of FIG. 1A, and for convenience of description and observation,FIG. 2A only schematically shows a portion of the components. FIG. 2B isa partial top view of the bottom surface of the conductive via and thefirst circuit layer in the region R of FIG. 1A, and for convenience ofdescription and observation, FIG. 2B only schematically shows a portionof the components. Referring to FIG. 1 and FIG. 2A, FIG. 2A illustratesthe plane where the pads 132 located on the insulating adhesive layer140 in the region R. The pad 132 (shown in FIG. 1K) has a top surface132T. In the present embodiment, since the first substrate 100 is, forexample, a redistribution layer (RDL) using ultra-fine line technology,therefore the conductive structures 130 may have fine pitchestherebetween. For example, a spacing W1 between any two of the adjacentpads 132 of the conductive structures 130 may be less than or equal to60 microns. In some embodiments, the minimum spacing W1 between any twoof the adjacent pads 132 may selectively be 10 microns to 60 microns.

Referring to FIG. 1 and FIG. 2B, FIG. 2B illustrates the interface ofthe insulating layer 120 at where the conductive via 134 contacts thefirst circuit layer 110 in the region R. The conductive via 134 (shownin FIG. 1K) has a bottom surface 134B. In the present embodiment, adiameter D2 of the bottom surface 134B may be less than or equal to 30microns.

In some embodiments, the diameter D2 of the bottom surface 134B canselectively be 10 microns to 30 microns. The linewidth D1 of the firstcircuit layer 110 may be less than or equal to the diameter D2 of thebottom surface 134B.

With the above arrangement, referring to FIG. 1, FIG. 2A and FIG. 2B, anorthographic projection of the conductive via 134 contacting the bottomsurface 134B of the first circuit layer 110 on the second substrate 200may be located within an orthographic projection of the top surface 132Tof the pad 132 on the second substrate 200. In other words, thecross-sectional shape of the conductive via 134 is, for example, ataper, and the portion which contacts the pad 132 has a larger area, andthe portion which contacts the first circuit layer 110 has a smallerarea. As such, the first circuit layer 110 may have a good design marginunder the design of an ultra-fine line manufacturing process.

It should be noted that the circuit carrier board 1 according to anembodiment of the present invention is a redistribution layer using theultra-fine line technology. Therefore, the circuit carrier board 1 hasthe first circuit layer 110 having an ultra-fine linewidth and the pads132 disposed with fine pitch. Under the above arrangement, theelectronic elements 300 (including the first electronic element 310 andthe second electronic element 320) having high density circuits can bedirectly electrically connected to the pads 132 and through the firstcircuit layer. 110 to achieve interconnection between electronicelements 300. In other words, the circuit carrier board 1 is adapted tointerconnect the plurality of the electronic components 300 with highdensity circuits, thereby reducing signal delay and improving theperformance of the circuit carrier board 1.

In addition, the electronic elements 300 can also be directlyelectrically connected to the second conductive layers 210 (includingthe topmost layer 211 and the bottommost layer 212) of the secondsubstrate 200 through the first conductive layer 100 of the firstsubstrate 100. Therefore, in addition to the first substrate 100 havingthe ultra-fine linewidth can be bonded to the entire surface of thesecond substrate 200, and thus simplify the manufacturing process andincrease the wiring margin of the circuit carrier board 1. Furthermore,the build-up layers formed by the dielectric layers 220 of the secondsubstrate 200 may be used to supports the first substrate 100, therebyimproving the overall rigidity the reliability of the structure of thecircuit carrier board 1.

In short, in the manufacturing method of the circuit carrier board 1 ofthe present embodiment, since the second substrate 200 having a normallinewidth can be directly formed and bonded to the entire surface of thefirst substrate 100 having the first circuit layer 110 with theultra-fine linewidth. Therefore, the first circuit layer 110 and thesecond circuit layer 120 made of different fineness in linewidth can bedirectly integrated onto the circuit carrier board 1, which simplifiesthe process, reduces the cost, and improves the wiring margin. Inaddition, the electronic elements 300 having high density circuits(including: the first electronic element 310 and the second electronicelement 320) can be directly electrically connected to the pads 132disposed with fine pitch on the first substrate 100. Under the abovearrangement, the electronic elements 300 can achieve interconnectivitythrough the first circuit layer 110. In this way, the circuit carrierboard 1 is adapted to interconnect the plurality of the electroniccomponents 300 with high density circuits, thereby reducing signal delayand improving the performance of the circuit carrier board 1. Inaddition, the second substrate 200 can further support the firstsubstrate 100, thereby improving the overall rigidity and thereliability of the structure of the circuit carrier board 1.

The following embodiments use the same reference numerals and parts inthe foregoing embodiments, wherein the same reference numerals are usedto refer to the same or similar elements. For the description of theparts omitted from the related art, reference may be made to theforegoing embodiments and is not repeated in the following embodiments.

FIG. 3A to FIG. 3K are cross-sectional views showing a manufacturingprocess of a circuit carrier board according to another embodiment ofthe invention. Referring to FIG. 1K and FIG. 3K, the circuit carrierboard 1A of the present embodiment is similar to the circuit carrierboard 1 of FIG. 1K. The main difference is that the circuit carrierboard 1A completes the disposition of the second substrate 200 first,and then completes the disposition of the conduction structure 130.Therefore, structural-wise, the first circuit layer 110 can be directlycovered by the insulating adhesive layer 140A to form the build-up layerof the first substrate 100A, so as to omit the additional use of theinsulating layer 120 (shown in FIG. 1K). A brief description of themanufacturing process of the circuit carrier board 1A will be describedin the following. The description of the same or similar components andsteps are not repeated.

Referring to FIG. 3A, the first circuit layer 110 is formed on the firsttemporary carrier board 10.

Referring to FIG. 3B, an insulating adhesive material 140′ is formed onthe first circuit layer 110 to form a first substrate 100″. In otherwords, the first substrate 100″ of the present embodiment includes abuild-up layer composed of the first circuit layer 110 and theinsulating adhesive material 140′, but the invention is not limitedthereto. In some embodiments, the first substrate 100″ may also includea plurality of build-up layers each formed by the first circuit layer110 and the insulating adhesive material 140″, and stacking the build-uplayers in sequence. The first substrate 100″ of the present embodimentis, for example, a substrate on which the conductive structures 130 arenot yet disposed on the exposed first circuit layer 110. In subsequentsteps, the conductive structures 130 are formed on the first substrate100A (shown in FIG. 31).

Referring to FIG. 3C and FIG. 3D, the first substrate 100″ is disposedon the second temporary carrier board 20. Next, the first temporarycarrier board 10 and the release layer 12 on the first temporary carrierboard 10 are removed.

Referring to FIG. 3E and FIG. 3F, the second substrate 200 is disposedon the surface 101A of the insulating adhesive material 140′ of thefirst substrate 100″. For example, the second substrate 200 includes aplurality of build-up layers (for example, two build-up layers) composedof the dielectric layers 220 and the second circuit layers 210. Indetail, after the dielectric layer 220 is disposed on the surface 101Aof the insulating material layer 140′, the topmost layer 211 of thesecond circuit layers 210 is formed to be electrically connected to thefirst circuit layer 110 through the contact windows (not labeled). Then,another dielectric layer 220 is overlaid on the topmost layer 211, andthen the bottommost layer 212 of the second circuit layer 210 is formedto be electrically connected to the topmost layer 211 through contactwindows (not shown). As shown in FIG. 3E and FIG. 3F, the insulatingadhesive material 140′ further has another surface 103A opposite to thesurface 101A, and the other surface 103A is located between theinsulating adhesive material 140′ and the second temporary carrier board20.

Referring to FIG. 3G, the second temporary carrier board 20 is removed,and the step of bonding the second substrate 200 to the first substrate100″ is completed.

Referring to FIG. 3G and FIG. 3H, a plurality of contact windows 142 areformed in the insulating adhesive material 140′ to form an insulatingadhesive layer 140A.

Referring to FIG. 31, a plurality of conductive structures 130 areformed in the insulating adhesive layer 140A. At this point, themanufacturing of the first substrate 100A is completed. In the presentembodiment, the first substrate 100A includes the first circuit layer110 embedded in the surface 101A of the insulating adhesive layer 140Aand the conductive structures 130 are disposed in the insulatingadhesive layer 140A. The pads 132 of the conductive structures 130 aredisposed on the other surface 103A. The contact windows 142 of theinsulating adhesive layer 140A expose the first circuit layer 110, andthe conductive vias 134 of the conductive structures 130 are filled inthe contact windows 142 to contact and electrically connect to the firstcircuit layer 110. In the present embodiment, the method of forming thecontact windows 142 includes photolithography, mechanical drilling,laser drilling, or other suitable methods, and the invention is notlimited thereto.

Referring to FIG. 3J, a plurality of solder resist layers SR arerespectively formed on the first substrate 100A and the second substrate200. In the present embodiment, the two solder resist layers SRpartially cover the conductive structure 130 on the first substrate 100Aand the bottommost layer 212 in the second circuit layers 210 on thesecond substrate 200 respectively.

Referring to FIG. 3K, a plurality of electronic elements 300 aredisposed on the first substrate 100 to be electrically connected to thepads 132 and the first circuit layer 110. In the present embodiment, theelectronic elements 300 include, for example, the first electronicelement 310 and the second electronic element 320, and the conductivebumps 311, 321 are respectively disposed on the first electronic element310 and the second electronic element 320 in high density. In thepresent embodiment, the first electronic element 310 and the secondelectronic element 320 further have solder balls 312, 322 respectivelydisposed on the conductive bumps 311, 321 , but the invention is notlimited thereto. The first electronic element 310 and the secondelectronic element 320 are electrically connected to the pads 132through the conductive bumps 311, 321 and the solder balls 312, 322.

Finally, a plurality of solder balls SB are disposed on the secondsubstrate 200 and electrically connected to the bottommost layer 212 ofthe second circuit layers 210. At this point, the manufacturing of thecircuit carrier board 1A has been completed. In the above arrangement,since the second substrate 200 can be formed on the insulating adhesivematerial 140′ of the first substrate 100A, and then the disposition theconductive structures 130 is completed. Therefore, the insulating layer120 can be replaced by the insulating adhesive layer 140A, which mayfurther simplify the manufacturing process, and save cost. In addition,with the above design, the circuit carrier board 1A of the presentembodiment can also achieve the same effects as the above embodiment,and thus will not be described herein.

FIG. 4 is a cross-sectional view of a circuit carrier board of yetanother embodiment of the invention. Referring to FIG. 1K and FIG. 4,the circuit carrier board 1B of the present embodiment is similar to thecircuit carrier board 1 of FIG. 1K. The main difference is that thecircuit carrier board 1B further includes a plurality of surface-treatedmetal pads 160. The metal pads 160, 260 are respectively in contact withand disposed on the pads 132 and the bottommost layer 212 of the secondcircuit layers 210. From another perspective, the metal pads 160 can belocated between the pads 132 and the solder balls 312, 322 of theelectronic elements 300 (including the first electronic element 310 andthe second electronic element 320). The metal pads 260 may be locatedbetween the bottommost layer 212 of the second circuit layers 210 andthe solder balls SB.

In the present embodiment, the method for forming the metal pads 160,260 includes surface treatment of the pads 132 and the bottommost layer212 of the second circuit layers 210. The surface treatment includeselectroless nickel/electroless palladium/immersion gold (ENEPIG),electroless nickel autocatalytic gold (ENAG), Immersion tin (IT),micro-ball, and 305 tin-silver-copper paste (SAC 305). In the abovearrangement, the metal pads 160, 260 can protect the pads 132 and thesecond circuit layer 210, and can also improve the conductivity of thepads 132 and the second circuit layer 210, thereby further improving theoverall performance of the circuit carrier board 1B. In addition, withthe above design, the circuit carrier board 1B of the present embodimentcan also achieve the same effects as the above embodiment, and thus willnot be described herein.

In summary, in the circuit carrier board and the manufacturing methodthereof according to an embodiment of the present invention, since thesecond substrate having a normal linewidth can be directly formed andbonded to the entire surface of the first substrate having the firstcircuit layer with the ultra-fine linewidth. Therefore, the firstcircuit layer and the second circuit layer made of different fineness inlinewidth can be directly integrated onto the circuit carrier board,which simplifies the manufacturing process, reduces the cost, andimproves the wiring margin. In addition, the electronic elements havinghigh density circuits (including: the first electronic element and thesecond electronic element) can be directly electrically connected to thepads disposed with fine pitch on the first substrate 100. Under theabove arrangement, the electronic elements can achieve interconnectivitythrough the first circuit layer. In this way, the circuit carrier boardis adapted to interconnect the plurality of the electronic componentswith high density circuits, thereby reducing signal delay and improvingthe performance of the circuit carrier board. In addition, the build-uplayers of the second substrate can further support the first substrate,thereby improving the overall rigidity and the reliability of thestructure of the circuit carrier board.

In addition, the circuit carrier board can also partially expose thepads through the insulating adhesive layer to increase the structuralreliability of the pad, and further protect the pads and the insulatinglayer. Furthermore, the insulating adhesive layer may have the effect ofsolder resist, thus allowing to omit the step of disposing the solderresist layer, and simplify the manufacturing process and save costs.

In addition, the manufacturing method of the circuit carrier board canalso complete the disposition of the second substrate first, and thencomplete the disposition of the conductive structures on the firstsubstrate. Therefore, the first circuit layer can be directly covered bythe insulating adhesive layer, thereby replacing the insulating layerand further simplifying the manufacturing process and saving cost.

Furthermore, the circuit carrier board may further include metal padsdisposed on the pads and the bottommost layer of the second circuitlayers. Therefore, the metal pads can protect the pads and the secondcircuit layer, and can also improve the conductivity of the pads and thesecond circuit layer, thereby further improving the overall performanceof the circuit carrier board.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodimentswithout departing from the scope or spirit of the disclosure. In view ofthe foregoing, it is intended that the disclosure covers modificationsand variations provided that they fall within the scope of the followingclaims and their equivalents.

What is claimed is:
 1. A manufacturing method of a circuit carrierboard, comprising: providing a first temporary carrier board; forming afirst substrate on the first temporary carrier board, wherein the firstsubstrate comprises a first circuit layer and a plurality of conductivestructures, and the conductive structures being adapted to beelectrically connected to a plurality of electronic elements; performinga bonding step of bonding the first substrate to a second temporarycarrier board, and the conductive structures are located between thefirst circuit layer and the second temporary carrier board; removing thefirst temporary carrier board; forming a second substrate on the firstsubstrate to bond the second substrate to the first substrate, whereinthe second substrate comprising: a plurality of dielectric layers; and aplurality of second circuit layers disposed in the dielectric layers,wherein a bottommost layer of the second circuit layers is exposedoutside of the dielectric layers, and a topmost layer of the secondcircuit layers is electrically connected to the first circuit layer; andremoving the second temporary carrier board.
 2. The manufacturing methodof the circuit carrier board according to claim 1, wherein the step offorming the first substrate comprises: forming a release layer on thefirst temporary carrier board; forming the first circuit layer on therelease layer; forming an insulating layer on the release layer andcovering the first circuit layer; forming the conductive structures onthe insulating layer, and the conductive structures are electricallyconnected to the first circuit layer; and Forming an insulating adhesivematerial on the insulating layer, and the conductive structures arelocated between the insulating adhesive material and the insulatinglayer.
 3. The manufacturing method of the circuit carrier boardaccording to claim 2, wherein the step of forming the first substratefurther comprises: performing a thinning process to remove a portion ofthe insulating adhesive material to form an insulating adhesive layerand exposing the conductive structures.
 4. The manufacturing method ofthe circuit carrier board according to claim 1, wherein the step offorming the second substrate comprises: forming the dielectric layersstacked on the first substrate in sequence; and forming the secondcircuit layers in the dielectric layers, and the second circuit layersare electrically connected to one another.
 5. The manufacturing methodof the circuit carrier board according to claim 4, wherein the secondsubstrate is disposed on the insulating layer.
 6. The manufacturingmethod of the circuit carrier board according to claim 1, wherein thestep of forming the first substrate comprises: forming a release layeron the first temporary carrier board; forming the first circuit layer onthe release layer; and forming an insulating adhesive material on thefirst circuit layer.
 7. The manufacturing method of the circuit carrierboard according to claim 6, wherein the second substrate is disposed onthe insulating adhesive material.
 8. The manufacturing method of thecircuit carrier board according to claim 6, wherein the step of formingthe first substrate further comprises: after the step of forming thesecond substrate on the first substrate, forming a plurality of contactwindows in the insulating adhesive material to form an insulatingadhesive layer; and forming the conductive structures in the insulatingadhesive layer, and the conductive structures are electrically connectedto the first circuit layer through the contact windows.
 9. Themanufacturing method of the circuit carrier board according to claim 1,further comprising: forming a plurality of solder resist layers on thefirst substrate and the second substrate respectively, wherein thesolder resist layers partially covering the conductive structures andthe bottommost layer of the second circuit layers; and disposing aplurality of solder balls and electrically connecting the solder ballsto the bottommost layer of the second circuit layers.